Project Structure & Workpackages description
The project was structured into seven complementary Work Packages (WP) related as shown in the PERT diagram to the right. The split of functionalities ensured complementarities of activities and partner’s background/know-how. The project has been led by Dr. Alain Mourad (Samsung UK), DAVINCI Project Coordinator.
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In order to facilitate the management within the different workpackages, each workpackage is divided into tasks which focus on a very specific topic. The public deliverables produced by each task can be found here.
The following table enumerates the different tasks within each workpackage as well as the Task Leaders.
Task Number |
Task Description |
Task Leader |
Affiliation |
T2.1 |
IMT-Advanced Candidates Analysis |
Ismael Gutierrez |
SEUK |
T2.2 |
Link Level Evaluation |
Joan Bas |
CTTC |
T2.3 |
System Level Evaluation |
Alain Mourad |
SEUK |
T3.1 |
Demonstration of DaVinci codec in 45nm technology |
Vincent Heinrich |
STM |
T3.2 |
Synthesis and mapping |
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T3.3 |
Wireless platform adaptation and wireless test |
Tom Huybrechts |
IMEC |
T4.1 |
Providing Benchmark non-binary LDPC codes to linked WPs |
Charly Poulliat |
ENSEA |
T4.2 |
Development and optimization of non-binary root-LDPC codes |
David Declercq |
ENSEA |
T4.3 |
Development and asymptotical study of non-binary-DGLDPC codes |
Charly Poulliat |
ENSEA |
T4.4 |
Optimization of NB-DGLDPC codes |
David Declercq |
ENSEA |
T4.5 |
Development of flexible coding schemes based on non-binary codes |
Charly Poulliat |
ENSEA |
T4.6 |
Performance comparison and Conclusion on the best code family |
David Declercq |
ENSEA |
T5.1 |
Selection of Adaptive Coding Schemes and Modulation Techniques |
Giacomo Bacci |
WISER |
T5.2 |
Development of Iterative (turbo) Algorithms for Channel Estimation |
Marco Luise |
WISER |
T5.3 |
Optimization of H-ARQ techniques and resource allocation |
Stephan Pfletschinger |
CTTC |
T5.4 |
Evaluating QoE of multimedia services |
Henryk Gierszal |
ITTI |
T5.5 |
All non-binary link adaptation strategy |
Inbar Fijalkow |
ENSEA |
T6.1 |
Architecture definition |
Laura Conde |
UBS |
T6.2 |
Development of generic VHDL model and |
Emmanuel Boutillon |
UBS |
T6.3 |
Find specific optimisation parameters for VLSI implementation |
Vincent Heinrich |
STM |
T6.4 |
Development of an ASIP |
Andre Bourdoux |
IMEC |
T7.1 |
Dissemination of Results |
Stephan Pfletschinger |
CTTC |
T7.2 |
Interface with Standardization and/or Regulatory Bodies |
Alain Mourad |
SEUK |
T7.3 |
Workshops/Seminars Organization |
Marco Luise |
WISER |

